When interpolation of use DDA law, v of speed of its interpolation feed not only the iteration frequency Fg with the system (namely clock frequency) into direct ratio, and still become inverse ratio with the capacity N of remainder register, the length L with straight line segment (or R of circular arc radius) into direct ratio. There is undermentioned relation to hold water between them: The V in type -- interpolation feed speed; -- systematic pulse equivalent; L -- the length of straight line segment; N -- the capacity of register; Fg -- iteration frequency. Apparent, although weave the speed of same size dictates, but the straight line segment that is aimed at different length, its feed speed is change (hypothesis Fg and N are fixed) , must try to try to improve. Improving a method commonly usedly is left move normalization and feed rate process designing (FRN) . By above example of interpolation of DDA circular arc can see, when interpolation Ⅰ quadrant goes against a circle when, y coordinate takes the lead in arriving. Be like direction of not compulsive Y to stop iteration at this moment, will appear out of tolerance, cannot arrive at correct terminus. To improve this one condition, register of commonly used remainder beforehand the way that buy figures will solve. Discuss below make DDA law is moved toward from the principle practical the speed that must solve and precision control problem. 1. Of feed speed turn measure equably -- left move normalization from afore-mentioned knowable, digital integrator spills over the frequency of pulse and register of the function that be accumulated put number mediumly to become direct ratio. When if use DDA,making linear interpolation, the time-interval of every block is changeless, because machine journey accident no matter, must finish M=2n likewise second cumulative operation. Distance of that is to say is long, take a knife fast; The distance is short, take a knife slow. So the feed speed of each block is abhorrent. Affected the exterior quality of treatment so, especially the block productivity with short distance is low. To overcome this one weakness, make spill over pulse is even, spill over rate rises, use normally left move normalization processing. Alleged " left move normalization " processing, it is the value when the function that be accumulated compares Xiaoshi, have I like register of the function that be accumulated before zero hour, be like direct iteration, need 2i second iteration at least so, ability output spills over pulse, the rate that causes output pulse falls. Because this is in actual digital integrator, in needing a register of the function that be accumulated before 0 move go be opposite namely be accumulated function comes true " left move normalization " processing. The course is different move the number of normalization becomes normalization to count -- the number in register its are the most exalted for " 1 " when, this number calls normalization number namely; Conversely the most exalted for " 0 " number calls blame normalization to count. Apparent, normalization number is cumulative spill over twice once surely, normalization of and rather than is counted must make above twice or for many times cumulative ability spills over once. 2. The measure that raises interpolation precision -- remainder register beforehand before buy is counted already remark, the interpolation error of DDA linear interpolation is less than equivalent of a pulse, but the interpolation error of interpolation of DDA circular arc is more than equivalent of a pulse likely, its reason is such: As a result of digital integrator spills over of the frequency of pulse and register of the function that be accumulated put number to become direct ratio, interpolation should undertake around reference axis when, the numerical value of the case that be accumulated of an integrator is close to Yu Ling, and the numerical value of the case that be accumulated of another integrator is close to maximum however (circular arc radius) , such, latter likelihood spills over continuously, and former did not spill over almost, of two integrator spill over pulse rate differs very big, cause curve of theory of interpolation contrail deviate (see a picture 2, 5) . To reduce interpolation error, raise interpolation precision, can the digit grow in quantity integrator, increase iteration number thereby. This is equivalent to a graph 2, T of the Δ between the Xiaoou with 7 integral rectangle is obtained smaller. Such doing can reduce interpolation error, but feed speed was reduced however, so we cannot increase the digit of register without limit. In actual integrator, often apply a kind handy and the method of effective -- remainder register beforehand buy number. It is namely before DDA interpolation, remainder register JRx and JRy beforehand buy some is numeric (either 0) , this one value can be most high capacity, namely 2n-1, also can be to be less than most the certain number of high capacity, be like 2n/2, commonly used is beforehand buy most high capacity is worth (call buy full number or full to load) and beforehand buy 0. 5 (call half to load) two kinds. "Half to load " it is to be before DDA iteration, the initial value of remainder register JRx and JRy is not buy 0, however buy 1000... 000 (namely 0.
5) , that is to say, the highest and significant position remainder register JRx and JRy " 1 " , the others everybody all buy " 0 " , such, as long as again overlay 0.
5, remainder register can produce the first to spill over pulse, make integrator spills over ahead of schedule. This is in the function that be accumulated is lesser, when cannot producing the situation that spill over tardy, have very great real sense, because it was improved,spill over the time of pulse distributings, reduced interpolation error. "Half to load " can make the error of linear interpolation reduces less than of half pulse equivalent, the example of a clearly is: If the start of linear OA is coordinate origin, terminal coordinate is A (15, 1) , not " half to load " when, x integrator did not spill over except first time iteration outside, 15 times iteration all has the rest spill over; And Y integrator just has when the 16th iteration only spill over pulse (see a picture 2, 17 (A) . If undertook " half to load " , criterion X integrator did not spill over except the 9th iteration outside, the others all has 15 times spill over; And of Y integrator spill over to have to the 8th iteration ahead of schedule spill over, this was improved spill over the time of pulse distributings, raised interpolation precision (see a picture 2, 17 (A) . Graph 2-17 " half to load " the contrail after " half to load " make the precision of circular arc interpolation gets clear improvement. Be like pair of graphs 2, 17 (B) example undertakes " half to load " , its interpolation contrail is like the broken line place in the graph to show, interpolation process sees a table 2, 7. After be being compared carefully, can discover, "Half to load " make of X integrator spill over pulse shifted to an earlier date, raised interpolation precision thereby. Alleged " full to load " , it is what to become the initial value place of remainder register JRx and JRy this register is in before DDA iteration most high capacity is worth (should be N when, namely buy enters 2n-1) , the generation of coordinate integrator in advance that this meeting makes numerical value of the case that be accumulated very little spills over, interpolation precision gets clear improvement. Graph 2-18 " full to load " the actual contrail after pursues 2, 18 it is to use " full to load " the interpolation contrail that the method gets, because be accumulated,function register and remainder register all are 3, buy is into the largest number 7 (111) . CNC Milling
